Institute of Information and Communication Technologies (ITACA)

DEFADAS

FPGA-based Accelerators for Sufficiently Reliable Deep Neural Networks for Automotive Systems

Autonomous vehicles are already technically feasible and evolving realities. Their intelligence lies in using deep learning neural networks (DNNs) that require higher computational capabilities and lower power consumption.

In recent years, reconfigurable logic (FPGAs) has made it possible to accelerate the execution of these DNNs by offering more complex and efficient hardware solutions that support upgrades for improvement, bug fixes or readjustment according to the vehicle’s operational circumstances, whether foreseen or not.

However, the ever-increasing cost and time-to-market reduction needs of the automotive industry, coupled with the human inability to deliver complex, error-free solutions, pose a challenge in ensuring these accelerators’ reliable and safe use for FPGA-based DNNs.

On the one hand, DEFADAS aims to design and implement adaptive fault-tolerant (TaF) strategies based on reconfigurable logic. The aim is not simply to tolerate the faults that could affect the evaluated accelerators but to allow them to change both their functional and TaF capabilities, depending on the needs, and without reprograming the whole system each time. In this way, we will be able to offer higher levels of protection, thus reducing the intensity with which hardware failures, especially those of the FPGAs themselves, which are increasing as the scales of integration increase, affect the processing of DNNs.

On the other hand, industry adoption of these new adaptive TaF mechanisms will largely depend on the ability of DEFADAS to verify and later certify their correct functioning under changing fault scenarios and operational situations. Fault injection techniques are privileged assessment tools in this context. However, most existing solutions assume hardware immutability, which makes them unsuitable in the DEFADAS research context and should be reviewed. Similarly, it should be remembered that the aim is to make the resulting accelerators more reliable and offer better performance, lower power consumption and lower cost. Therefore, It is necessary to benchmark the available alternatives and optimise their configuration on the basis of the results of this evaluation.

Proyecto PID2020-120271RB-I00 financiado por:

Logo Agencia Estatal de Investigación

Contact

Juan Carlos Ruiz García

Escuela Técnica Superior de Ingeniería Informática – Universitat Politècnica de València

Camino de Vera, s/n. Edificio 1G, planta 2. 46022 Valencia (Spain)

 

Phone +34 96 387 70 00 (Extension: 75752)

 

-> Send email

 

 

David de Andrés Martínez

Escuela Técnica Superior de Ingeniería Informática – Universitat Politècnica de València

Camino de Vera, s/n. Edificio 1G, planta 2. 46022 Valencia (Spain)

 

Phone +34 96 387 70 00 (Extension: 75752)

 

-> Send email

Projects Details

 

Funding:

AGENCIA ESTATAL DE INVESTIGACION

 

Project duration:

1 September 2021 – 31 August 2025

 

Official project website:

aplicat.upv.es/exploraupv/ficha-proyecto/proyecto/20210637