A team of researchers from the ITACA-UPV Institute has developed an innovative hybrid system that improves the reliability of SRAM memories in hostile environments and safety-critical applications.
This advance, published in the important IEEE Access journal of the Institute of Electrical and Electronics Engineers (IEEE), has been carried out by researchers Daniel Gil-Tomás, Luis J. Saiz-Adalid, Joaquín Gracia-Morán, J. Carlos Baraza-Calvo and Pedro J. Gil-Vicente.
SRAM memories, crucial in integrated circuit technologies, face important challenges due to Multiple-Bit Upsets (MBUs), potential errors caused by electromagnetic and high-energy particle radiation, which simultaneously affect multiple bits in a digital memory.
«MBUs can be a significant problem in integrated circuit technologies operating in hostile environments or critical applications in sectors such as aerospace, autonomous vehicles, nuclear plants, and even neural networks,» the study’s authors point out.
To address this challenge, ITACA-UPV researchers have combined two techniques that were used separately and that provide an efficient and highly reliable solution to transient faults in memory cells: DICE cells, known for their robustness, and error correction codes (ECC).
«This hybrid approach leverages the strengths of both techniques to provide greater tolerance to random MBUs with acceptable overhead,» the research authors highlight.
Promising Results
To evaluate the proposed technique, the correction capability was measured after different error injections, as well as the overhead of the memory and encoding/decoding circuits.
«The results are promising, as they offer high MBU correction coverage, which validates the effectiveness of the proposed design. This represents an advance in the reliability of SRAM memories by significantly improving safety and performance in critical applications,» indicate sources from the ITACA-UPV Institute.
In fact, the study shows that this new alternative not only provides greater error correction coverage but also improves memory access speed and reduces system complexity.
«With this innovative solution, sectors that rely on high-reliability technologies can expect a considerable improvement in protection against multiple errors, ensuring safer and more efficient operation of their systems,» conclude the researchers from the ITACA Institute at UPV.