{"id":16181,"date":"2024-05-31T06:42:52","date_gmt":"2024-05-31T06:42:52","guid":{"rendered":"https:\/\/www.itaca.upv.es\/stf\/researchers-at-the-itaca-upv-institute-develop-an-innovative-system-to-improve-the-reliability-of-sram-memories\/"},"modified":"2024-05-31T06:42:52","modified_gmt":"2024-05-31T06:42:52","slug":"researchers-at-the-itaca-upv-institute-develop-an-innovative-system-to-improve-the-reliability-of-sram-memories","status":"publish","type":"post","link":"https:\/\/www.itaca.upv.es\/stf\/researchers-at-the-itaca-upv-institute-develop-an-innovative-system-to-improve-the-reliability-of-sram-memories\/","title":{"rendered":"Researchers at the ITACA-UPV Institute develop an innovative system to improve the reliability of SRAM memories"},"content":{"rendered":"\n<p class=\"wp-block-paragraph\">A team of researchers from the ITACA-UPV Institute has developed an innovative <strong>hybrid system that improves the reliability of SRAM memories<\/strong> in hostile environments and safety-critical applications.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">This advance, published in the important IEEE Access journal of the <em>Institute of Electrical and Electronics Engineers (IEEE),<\/em> has been carried out by researchers Daniel Gil-Tom\u00e1s, Luis J. Saiz-Adalid, Joaqu\u00edn Gracia-Mor\u00e1n, J. Carlos Baraza-Calvo and Pedro J. Gil-Vicente.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">SRAM memories, crucial in integrated circuit technologies, face <strong>important challenges due to Multiple-Bit Upsets (MBUs)<\/strong>, potential errors caused by electromagnetic and high-energy particle radiation, which simultaneously affect multiple bits in a digital memory.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\u00abMBUs can be a significant problem in integrated circuit technologies operating in hostile environments or critical applications in sectors such as aerospace, autonomous vehicles, nuclear plants, and even neural networks,\u00bb the study&#8217;s authors point out.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">To address this challenge, ITACA-UPV researchers <strong>have combined two techniques that were used separately and that provide an efficient and highly reliable solution to transient faults in memory cells<\/strong>: DICE cells, known for their robustness, and error correction codes (ECC).<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\u00abThis hybrid <strong>approach leverages the strengths of both techniques<\/strong> to provide greater tolerance to random MBUs with acceptable overhead,\u00bb the research authors highlight.<\/p>\n\n\n\n<p class=\"has-medium-font-size wp-block-paragraph\"><strong>Promising Results <\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">To evaluate the proposed technique, the correction capability was measured after different error injections, as well as the overhead of the memory and encoding\/decoding circuits.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\u00abThe results are promising, as they offer high MBU correction coverage, which validates the effectiveness of the proposed design. This represents <strong>an advance in the reliability of SRAM memories by significantly improving safety and performance in critical applications<\/strong>,\u00bb indicate sources from the ITACA-UPV Institute.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">In fact, the study shows that this new alternative not only provides greater error correction coverage b<strong>ut also improves memory access speed and reduces system complexity.<\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\u00abWith this innovative solution, sectors that rely on high-reliability technologies can expect a considerable improvement in protection against multiple errors, ensuring safer and more efficient operation of their systems,\u00bb conclude the researchers from the ITACA Institute at UPV.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong><a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/10534066\/authors#authors\" target=\"_blank\" rel=\"noreferrer noopener\">Full article here:<\/a><\/strong><\/p>\n","protected":false},"excerpt":{"rendered":"<p>The proposal combines two techniques that were used separately and provide an efficient and highly reliable solution: DICE cells and error correction codes (ECC).<\/p>\n","protected":false},"author":0,"featured_media":16182,"comment_status":"","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_et_pb_use_builder":"","_et_pb_old_content":"","_et_gb_content_width":"","footnotes":""},"categories":[58],"tags":[],"class_list":["post-16181","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news-stf"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v28.7 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Researchers at the ITACA-UPV Institute develop an innovative system to improve the reliability of SRAM memories | ITACA STF<\/title>\n<meta name=\"robots\" content=\"index, follow, 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